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kjg0724
5d88781f74
core: add platform-specific SIMD for cv::reduce REDUCE_SUM ### Pull Request Rewrite `cv::reduce` SIMD optimization using platform-specific instructions as discussed in #28763. #### Changes **Col reduce (dim=1) — horizontal sum per row:** - ARM DOTPROD: `vdotq_u32()` — single-instruction byte sum, no intermediate flush needed - ARM AArch64 fallback: `vpaddlq` chain (u8→u16→u32) - Intel AVX2: `_mm256_sad_epu8()` — 32 bytes → 4×u64 partial sums per cycle - Intel SSSE3: `_mm_shuffle_epi8` + `_mm_sad_epu8` for cn=4 channel separation - Intel SSE2: `_mm_sad_epu8` for cn=1 - cn=4: hardware deinterleave (`vld4q_u8` on ARM, shuffle+SAD on Intel) **Row reduce (dim=0) — vertical accumulation across rows:** - u16 intermediate accumulator with 256-row flush (halves memory bandwidth vs direct u32) - ARM AArch64: `vaddw_u8` widening add (single instruction vs expand+add) - Intel: unpack + add with u16 buffer **Coverage:** All REDUCE_SUM type combinations — 8U→32S, 8U→32F, 16U→32F, 16S→32F, 32F→32F, 32F→64F, 64F→64F. Non-8U types use universal intrinsics where platform-specific gain is minimal (widening is single-stage, FP has limited alternatives). `REDUCE_AVG` benefits automatically (uses SUM internally). **Dispatch:** `CV_CPU_DISPATCH` with SSE2/AVX2/NEON_DOTPROD/LASX. Fallback hierarchy: DOTPROD → AArch64 NEON → Universal Intrinsics → scalar. #### Benchmark (Apple M3 Pro, MacBook Pro 16-inch 2023) | Path | Type | Speedup vs scalar | |------|------|-------------------| | Col reduce (dim=1) | 8UC1 | **3.0–4.5x** | | Col reduce (dim=1) | 8UC4 | **2.7–5.0x** | | Col reduce (dim=1) | 32FC1 | 1.7–2.3x | | Row reduce (dim=0) | 8UC1 | 1.1–1.5x | Row reduce gains are modest due to memory-bandwidth bound (as expected for vertical accumulation). No regressions on non-target paths (MAX, MIN, SUM2). #### Testing - `opencv_test_core --gtest_filter="*Reduce*:*reduce*"` — 483 tests PASSED - Edge cases: non-aligned dimensions (127×61), cn=2/3 scalar fallback, REDUCE_SUM2 unmodified #### Files changed - `modules/core/src/reduce.simd.hpp` — new, platform-dispatched SIMD implementation - `modules/core/src/reduce.dispatch.cpp` — new, CV_CPU_DISPATCH wrapper - `modules/core/CMakeLists.txt` — add `NEON_DOTPROD` to dispatch list - `modules/core/src/matrix_operations.cpp` — wire dispatch functions into ReduceC/R_Invoker