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https://github.com/opencv/opencv.git
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Abhishek Gola
bdf348c13a
Added MLAS third party module and integrated into GeMM path #28934 ### Pull Request Readiness Checklist See details at https://github.com/opencv/opencv/wiki/How_to_contribute#making-a-good-pull-request - [x] I agree to contribute to the project under Apache 2 License. - [x] To the best of my knowledge, the proposed patch is not based on a code under GPL or another license that is incompatible with OpenCV - [x] The PR is proposed to the proper branch - [x] There is a reference to the original bug report and related work - [x] There is accuracy test, performance test and test data in opencv_extra repository, if applicable Patch to opencv_extra has the same branch name. - [x] The feature is well documented and sample code can be built with the project CMake
248 lines
4.4 KiB
ArmAsm
248 lines
4.4 KiB
ArmAsm
/*++
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Copyright (c) Microsoft Corporation. All rights reserved.
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Licensed under the MIT License.
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Module Name:
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SgemmKernelPackA.S
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Abstract:
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This module implements the POWER10 kernel for packing matrix A for single precision SGEMM.
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This implementation targets power10 using VSX instructions.
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--*/
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/*++
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Routine Description:
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This routine is an inner kernel to pack matrix A for rows 4 or 8.
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Arguments:
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D (r3) - Supplies the address of Packed A.
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A (r4) - Supplies the address of matrix A.
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lda (r5) - LDA.
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k (r6) - Supplies the number of columns from matrix A.
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RowCount (r7) - Supplies the number of rows to process.
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Return Value:
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None.
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--*/
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#include "asmmacro.h"
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.text
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FUNCTION_ENTRY PackAKernelPOWER10
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slwi 9,5,2
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cmpldi 7,8
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add 8,4,9
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add 10,8,9
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add 11,10,9
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dcbt 0,4
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dcbt 0,8
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dcbt 0,10
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dcbt 0,11
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blt L_loop
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L_Rows8:
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lxvp 32,0(4)
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lxvp 42,32(4)
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addi 4,4,64
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dcbt 0,4
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lxvp 34,0(8) //a+lda
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lxvp 44,32(8) //a+32+lda
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lxvp 36,0(10) //a+2*lda
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lxvp 46,32(10) //a+32+2*lda
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lxvp 38,0(11) //a+3*lda
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lxvp 48,32(11) //a+32+3*lda
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add 7,11,9
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dcbt 0,7
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add 8,7,9
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dcbt 0,8
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add 10,8,9
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dcbt 0,10
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add 11,10,9
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dcbt 0,11
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vmrgow 8,3,1
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vmrgew 18,3,1
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vmrgow 9,7,5
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vmrgew 19,7,5
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xxpermdi 1,41,40,3
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xxpermdi 0,51,50,3
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xxpermdi 3,41,40,0
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xxpermdi 2,51,50,0
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vmrgow 8,2,0
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vmrgow 9,6,4
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vmrgew 18,2,0
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vmrgew 19,6,4
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stxvp 0,0(3)
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xxpermdi 9,41,40,3
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xxpermdi 8,51,50,3
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xxpermdi 11,41,40,0
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xxpermdi 10,51,50,0
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stxvp 2,32(3)
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stxvp 8,128(3)
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stxvp 10,160(3)
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vmrgow 0,13,11
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vmrgow 1,17,15
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vmrgew 18,13,11
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vmrgew 19,17,15
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xxpermdi 5,33,32,3
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xxpermdi 7,33,32,0
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xxpermdi 4,51,50,3
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xxpermdi 6,51,50,0
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vmrgow 0,12,10
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vmrgow 1,16,14
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stxvp 4,256(3)
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stxvp 6,288(3)
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vmrgew 18,12,10
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vmrgew 19,16,14
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xxpermdi 9,33,32,3
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xxpermdi 8,51,50,3
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xxpermdi 11,33,32,0
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xxpermdi 10,51,50,0
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lxvp 32,0(7) //a+4*lda
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lxvp 34,0(8) //a+5*lda
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lxvp 36,0(10) //a+6*lda
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lxvp 38, 0(11) //a+7*lda
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stxvp 8,384(3)
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stxvp 10,416(3)
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lxvp 42,32(7) //a+32+4*lda
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vmrgow 8,3,1
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vmrgew 18,3,1
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vmrgow 9,7,5
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vmrgew 19,7,5
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lxvp 44,32(8) //a+32+5*lda
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lxvp 46,32(10) //a+32+6*lda
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xxpermdi 1,41,40,3
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xxpermdi 0,51,50,3
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xxpermdi 3,41,40,0
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xxpermdi 2,51,50,0
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lxvp 48,32(11) //a+32+7*lda
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add 8,4,9
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dcbt 0,8
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add 10,8,9
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dcbt 0,10
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add 11,10,9
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dcbt 0,11
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stxvp 0,64(3)
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stxvp 2,96(3)
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vmrgow 8,2,0
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vmrgow 9,6,4
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vmrgew 18,2,0
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vmrgew 19,6,4
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vmrgow 0,13,11
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vmrgow 1,17,15
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xxpermdi 9,41,40,3
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xxpermdi 8,51,50,3
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xxpermdi 11,41,40,0
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xxpermdi 10,51,50,0
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vmrgew 18,13,11
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vmrgew 19,17,15
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stxvp 8,192(3)
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stxvp 10,224(3)
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xxpermdi 5,33,32,3
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xxpermdi 4,51,50,3
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xxpermdi 7,33,32,0
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xxpermdi 6,51,50,0
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vmrgow 0,12,10
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vmrgow 1,16,14
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stxvp 4,320(3)
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stxvp 6,352(3)
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vmrgew 18,12,10
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vmrgew 19,16,14
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xxpermdi 9,33,32,3
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xxpermdi 8,51,50,3
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xxpermdi 11,33,32,0
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xxpermdi 10,51,50,0
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stxvp 8,448(3)
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stxvp 10,480(3)
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addi 6,6,-16
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cmpldi 6,16
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addi 3,3,512
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bge L_Rows8
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b L_exit
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L_loop:
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lxvp 32,0(4)
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lxvp 42,32(4)
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addi 4,4,64
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dcbt 0,4
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lxvp 34,0(8) //a+lda
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lxvp 44,32(8) //a+32+lda
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lxvp 36,0(10) //a+2*lda
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lxvp 46,32(10) //a+32+2*lda
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lxvp 38,0(11) //a+3*lda
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lxvp 48,32(11) //a+32+3*lda
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vmrgow 8,3,1
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vmrgew 18,3,1
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vmrgow 9,7,5
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vmrgew 19,7,5
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add 8,4,9
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dcbt 0,8
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add 10,8,9
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dcbt 0,10
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add 11,10,9
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dcbt 0,11
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xxpermdi 1,41,40,3
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xxpermdi 0,51,50,3
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xxpermdi 3,41,40,0
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xxpermdi 2,51,50,0
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vmrgow 8,2,0
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vmrgow 9,6,4
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vmrgew 18,2,0
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vmrgew 19,6,4
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stxvp 0,0(3)
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xxpermdi 9,41,40,3
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xxpermdi 8,51,50,3
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xxpermdi 11,41,40,0
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xxpermdi 10,51,50,0
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stxvp 2,32(3)
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stxvp 8,64(3)
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stxvp 10,96(3)
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vmrgow 0,13,11
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vmrgow 1,17,15
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vmrgew 18,13,11
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vmrgew 19,17,15
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xxpermdi 5,33,32,3
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xxpermdi 7,33,32,0
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xxpermdi 4,51,50,3
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xxpermdi 6,51,50,0
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vmrgow 0,12,10
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vmrgow 1,16,14
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stxvp 4,128(3)
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stxvp 6,160(3)
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vmrgew 18,12,10
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vmrgew 19,16,14
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xxpermdi 9,33,32,3
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xxpermdi 8,51,50,3
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xxpermdi 11,33,32,0
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xxpermdi 10,51,50,0
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stxvp 8,192(3)
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stxvp 10,224(3)
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addi 3,3,256
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addi 6,6,-16
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cmpldi 6,16
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bge L_loop
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L_exit:
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blr
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