mirror of
https://github.com/opencv/opencv.git
synced 2026-07-30 15:53:03 +04:00
Alexander Smorkalov
e3fe5a5681
Merge pull request #28112 from asmorkalov:as/jpeg_turbo_3.1.2 ### Pull Request Readiness Checklist Previous update: https://github.com/opencv/opencv/pull/27031 See details at https://github.com/opencv/opencv/wiki/How_to_contribute#making-a-good-pull-request - [x] I agree to contribute to the project under Apache 2 License. - [x] To the best of my knowledge, the proposed patch is not based on a code under GPL or another license that is incompatible with OpenCV - [ ] The PR is proposed to the proper branch - [ ] There is a reference to the original bug report and related work - [ ] There is accuracy test, performance test and test data in opencv_extra repository, if applicable Patch to opencv_extra has the same branch name. - [ ] The feature is well documented and sample code can be built with the project CMake
87 lines
2.3 KiB
NASM
87 lines
2.3 KiB
NASM
;
|
|
; SIMD instruction support check
|
|
;
|
|
; Copyright 2009 Pierre Ossman <ossman@cendio.se> for Cendio AB
|
|
; Copyright (C) 2016, D. R. Commander.
|
|
; Copyright (C) 2023, Aliaksiej Kandracienka.
|
|
;
|
|
; Based on
|
|
; x86 SIMD extension for IJG JPEG library
|
|
; Copyright (C) 1999-2006, MIYASAKA Masaru.
|
|
; For conditions of distribution and use, see copyright notice in jsimdext.inc
|
|
;
|
|
; This file should be assembled with NASM (Netwide Assembler) or Yasm.
|
|
|
|
%include "jsimdext.inc"
|
|
|
|
; --------------------------------------------------------------------------
|
|
SECTION SEG_TEXT
|
|
BITS 64
|
|
;
|
|
; Check if the CPU supports SIMD instructions
|
|
;
|
|
; GLOBAL(unsigned int)
|
|
; jpeg_simd_cpu_support(void)
|
|
;
|
|
|
|
align 32
|
|
GLOBAL_FUNCTION(jpeg_simd_cpu_support)
|
|
|
|
EXTN(jpeg_simd_cpu_support):
|
|
push rbp
|
|
mov rbp, rsp
|
|
push rbx
|
|
push rdi
|
|
|
|
xor rdi, rdi ; simd support flag
|
|
|
|
; Assume that all x86-64 processors support SSE & SSE2 instructions
|
|
or rdi, JSIMD_SSE2
|
|
or rdi, JSIMD_SSE
|
|
|
|
; Check whether CPUID leaf 07H is supported
|
|
; (leaf 07H is used to check for AVX2 instruction support)
|
|
mov rax, 0
|
|
cpuid
|
|
cmp rax, 7
|
|
jl short .return ; Maximum leaf < 07H
|
|
|
|
; Check for AVX2 instruction support
|
|
mov rax, 7
|
|
xor rcx, rcx
|
|
cpuid
|
|
mov rax, rbx ; rax = Extended feature flags
|
|
|
|
test rax, 1<<5 ; bit5:AVX2
|
|
jz short .return
|
|
|
|
; Check for AVX2 O/S support
|
|
mov rax, 1
|
|
xor rcx, rcx
|
|
cpuid
|
|
test rcx, 1<<27
|
|
jz short .return ; O/S does not support XSAVE
|
|
test rcx, 1<<28
|
|
jz short .return ; CPU does not support AVX2
|
|
|
|
xor rcx, rcx
|
|
xgetbv
|
|
and rax, 6
|
|
cmp rax, 6 ; O/S does not manage XMM/YMM state
|
|
; using XSAVE
|
|
jnz short .return
|
|
|
|
or rdi, JSIMD_AVX2
|
|
|
|
.return:
|
|
mov rax, rdi
|
|
|
|
pop rdi
|
|
pop rbx
|
|
pop rbp
|
|
ret
|
|
|
|
; For some reason, the OS X linker does not honor the request to align the
|
|
; segment unless we do this.
|
|
align 32
|