Restricting the condition with _M_IX86/_M_X64 so it only applies to x86/x64 MSVC builds. MSVC ARM64 now falls through to the existing `#else` branch, which already has a portable CV_SIMD-based exp32f/exp64f implementation
**Performance Benchmarks:**
<img width="976" height="486" alt="image" src="https://github.com/user-attachments/assets/62daf2c3-34ac-4fc7-92d0-268073f746f3" />
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More use of AutoBuffer #28907
When possible, AutoBuffer should be faster than std::vector<>, and should not be worse if it requires a heap allocation rather than a stack allocation.
### Pull Request Readiness Checklist
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core(opengl): fix memory leak in OpenCL extensions gathering #28981
## Problem
Fixes#28980
In `modules/core/src/opengl.cpp`, inside `initializeContextFromGL()`, a `char[]` buffer is allocated to query OpenCL device extensions:
```cpp
extensions = new char[extensionSize];
status = clGetDeviceInfo(..., extensions, &extensionSize);
if (status != CL_SUCCESS)
continue; // leaks `extensions`
```
When `clGetDeviceInfo()` fails, `continue` skips the corresponding `delete[]` on the success path, causing the allocated buffer to leak.
Additionally, the `catch (...)` block also bypasses cleanup, so any thrown exception leaks the buffer as well.
## Fix
Replace the raw `char*` allocation with `std::unique_ptr<char[]>`.
This ensures the buffer is automatically released on all exit paths, including:
- normal execution
- early `continue`
- exception handling paths
## Checklist
- [x] I agree to contribute to the project under the Apache 2 License.
- [x] To the best of my knowledge, the proposed patch is not based on code under GPL or another license incompatible with OpenCV.
- [x] The PR is proposed to the proper branch (`4.x`).
- [x] There is a reference to the original bug report and related work, if applicable.
- [x] Accuracy/performance tests and test data in `opencv_extra` are included, if applicable.
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core: fix inverted continuity check in cvReshapeMatND() #29132
### Pull Request Readiness Checklist
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Better Durand-Kerner Initialization #29109
While investigating issue #23644, I have found [this paper](https://link.springer.com/article/10.1007/BF01935059) which presents a good initialization for the Durand-Kerner algorithm. Basically the idea is to put the initial points equidistantly on a circle on the complex plane. The radius of the circle is computed as
<img width="607" height="178" alt="image" src="https://github.com/user-attachments/assets/ea31b002-c924-4b93-9334-3e59597c896b" />
Note that the $a_i$ coefficients in that paper are reversed compared to OpenCV. That's where the `(n - i)` in the code comes from.
I have implemented just the mean of the $u_i$'s for the sake of simplicity. That's already enough to make the algorithm converge in all cases I have tested. I have used this to test for convergence for many polynomials of order 2 and 4 and coefficients of different magnitudes:
```cpp
TEST(Core_SolvePoly, large_test)
{
cv::Mat_<float> coefs3(1,3);
cv::Mat_<float> coefs5(1,5);
cv::Mat r;
double prec;
for (int c0 = -20; c0 <= 20; c0++)
{
coefs3.at<float>(0) = c0;
for (int c1 = -20; c1 <= 20; c1++)
{
coefs3.at<float>(1) = c1;
for (int c2 = -20; c2 <= 20; c2++)
{
coefs3.at<float>(2) = c2;
prec = cv::solvePoly(coefs3, r);
EXPECT_LE(prec, 1e-6);
}
}
}
for (int c0 = -10; c0 <= 10; c0++)
{
coefs5.at<float>(0) = c0;
for (int c1 = -10; c1 <= 10; c1++)
{
coefs5.at<float>(1) = c1;
for (int c2 = -10; c2 <= 10; c2++)
{
coefs5.at<float>(2) = c2;
for (int c3 = -10; c3 <= 10; c3++)
{
coefs5.at<float>(3) = c3;
for (int c4 = -10; c4 <= 10; c4++)
{
coefs5.at<float>(4) = c4;
prec = cv::solvePoly(coefs5, r);
EXPECT_LE(prec, 1e-2);
}
}
}
}
}
for (int i = -10; i < 10; i++)
{
coefs3.at<float>(0) = pow(2, i);
for (int j = -10; j < 10; j++)
{
coefs3.at<float>(1) = pow(2, j);
for (int k = -10; k < 10; k++)
{
coefs3.at<float>(2) = pow(2, k);
prec = cv::solvePoly(coefs3, r);
EXPECT_LE(prec, 1e-6);
}
}
}
}
```
This test passes, but I have not committed it because it runs for a couple of seconds.
This fixes#23644 and replaces #29055. I have checked #29055 and it does not pass the test above. It seems to be optimized to the precise polynomial of #23644.
### Pull Request Readiness Checklist
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core(rvv): fix v_matmul/v_matmuladd scalable semantics and expand lane-group test coverage #29080
### Pull Request Readiness Checklist
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## Platform
SpacemiT X60 (K1), 8-core RISC-V RVV 1.0, VLEN=256, 16GB RAM, OS: Bianbu Linux (kernel 6.6.63), GCC 13.2.0, Build: OpenCV 4.14.0-pre, Release, HAL: YES (RVV HAL 0.0.1)
## Motivation
OpenCV's Universal Intrinsics `v_matmul` and `v_matmuladd` have a semantic bug in the RVV scalable backend (`modules/core/include/opencv2/core/hal/intrin_rvv_scalable.hpp`).
The current implementation uses `v_extract_n(v, 0/1/2/3)` with hardcoded indices, assuming the vector holds exactly 4 float lanes (128-bit fixed). On hardware with VLEN=256 (e.g. SpacemiT K1 / BPI-F3), `v_float32` with LMUL=2 holds 16 lanes. As a result, lanes 4–15 silently reuse the inputs from lanes 0–3, producing wrong results.
OpenCV itself acknowledges this in `modules/core/src/matmul.simd.hpp`:
// v_matmuladd for RVV is 128-bit only but not scalable,
// this will fail the test Core_Transform.accuracy
The RVV scalable `transform_32f` path has been disabled because of this bug. However, the existing `TheTest<R>::test_matmul()` only checked the first 4-lane group (the outer loop was effectively hardcoded to `int i = 0`), so the bug was never caught by CI even on wide-vector backends.
## Modification
**Test fix** (`modules/core/test/test_intrin_utils.hpp`): Expanded `test_matmul()` to iterate over all 4-lane groups:
// Before (only checked lane group i=0)
int i = 0;
for (int j = i; j < i + 4; ++j) { ... }
// After (checks all lane groups)
for (int i = 0; i < VTraits<R>::vlanes(); i += 4)
{
for (int j = i; j < i + 4; ++j) { ... }
}
**Kernel fix** (`modules/core/include/opencv2/core/hal/intrin_rvv_scalable.hpp`): Rewrote `v_matmul` and `v_matmuladd` to process all 4-lane groups correctly. Each group of 4 lanes now independently computes the full matrix multiply using its own `v[i], v[i+1], v[i+2], v[i+3]` inputs. The `transform_32f` RVV path in `matmul.simd.hpp` remains disabled as the autovectorized path shows better performance on current hardware.
## Experiment 1: Bug reproduced on SpacemiT K1 (VLEN=256)
./opencv_test_core --gtest_filter="*intrin*"
Result: `hal_intrin128.float32x4_BASELINE` FAILED with 24 failures, all from lane groups i=4, i=8, i=12 (lanes 4–15).
Representative failures from `v_matmul` (line 1526):
i=4 j=4: actual=158 expected=56
i=4 j=5: actual=166.39999 expected=59.200001
i=8 j=8: actual=314.39999 expected=68.800003
i=12 j=12: actual=512.40002 expected=81.599998
Representative failures from `v_matmuladd` (line 1540):
i=4 j=4: actual=147.5 expected=51.5
i=8 j=8: actual=284.70001 expected=60.700001
i=12 j=12: actual=453.89999 expected=69.900002
Lane group i=0 (j=0..3) passed correctly — confirming the bug only affects lanes beyond the first 4, exactly as expected from the hardcoded `v_extract_n(v, 0/1/2/3)` implementation.
## Experiment 2: Both tests pass after fixing the kernel
./opencv_test_core --gtest_filter='hal_intrin128.float32x4_BASELINE'
[ OK ] hal_intrin128.float32x4_BASELINE (1859 ms)
[ PASSED ] 1 test.
./opencv_test_core --gtest_filter='Core_Transform.accuracy'
[ OK ] Core_Transform.accuracy (819 ms)
[ PASSED ] 1 test.
## Experiment 3: RVV transform path remains disabled (performance regression)
After re-enabling the RVV scalable `transform_32f` path experimentally, benchmarks showed a significant regression vs the compiler-autovectorized scalar path (CV_32FC3):
Size RVV path Scalar path Ratio
640x480 7.83 ms 1.48 ms 5.3x slower
1280x720 23.96 ms 5.17 ms 4.6x slower
1920x1080 53.76 ms 10.12 ms 5.3x slower
The compiler-autovectorized path outperforms the hand-written RVV kernel for this workload, consistent with the original comment in `matmul.simd.hpp`. The `transform_32f` RVV path is therefore kept disabled in this PR. The kernel fix to `v_matmul`/`v_matmuladd` remains necessary for correctness on wide-vector hardware, and the expanded test ensures the bug cannot regress silently in future.
Rvv core norm #29057Fixesopencv/opencv#29052
### Problem
`Core_Norm/ElemWiseTest.accuracy/0` failed on RISC-V with RVV enabled when computing norm for `CV_16S` data.
The reported failing case was:
```text
src[0] ~ 16sC4 3-dim (1 x 116 x 40)
```
The expected norm result was a large positive `double`, but the RVV path returned an incorrect value:
```text
expected: 3370900308417
actual: -173296
```
This indicates that the problem was not in the public `cv::norm()` API, but in the RVV HAL implementation used for the `CV_16S` L2/L2SQR accumulation path.
### Root Cause
The RVV HAL has a specialized implementation for `CV_16S` L2 norm:
```cpp
NormL2_RVV<short, double>
```
The implementation widens `int16` values, squares them, converts the widened products to `float64`, accumulates them in an `f64m8` vector, and finally reduces the vector to a scalar `double`:
```cpp
auto s = __riscv_vfmv_v_f_f64m8(0, vlmax);
...
auto v_mul = __riscv_vwmul(v, v, vl);
s = __riscv_vfadd_tu(s, s, __riscv_vfwcvt_f(v_mul, vl), vl);
...
return __riscv_vfmv_f(__riscv_vfredosum(...));
```
The bug was in the scalar initializer passed to `__riscv_vfredosum`.
Before this patch, the code created an `f64m1` scalar vector but used the maximum vector length for `e32m1`:
```cpp
__riscv_vfmv_s_f_f64m1(0, __riscv_vsetvlmax_e32m1())
```
This is inconsistent: the vector type is `f64m1`, so the VL used to initialize it must correspond to `e64m1`, not `e32m1`.
Add ARMPL support for DFT Function #28664
- This PR introduces hal/armpl/ with implementation of 1D, 2D DFT and DCT routines using ARM Performance Libraries as a custom HAL replacement for OpenCV's DFT & DCT Function.
- ArmPL MSI package is automatically downloaded and extracted via CMake when building on Windows ARM64, with a WITH_ARMPL option that defaults to ON for that platform.
- Forward and inverse real DFT calls in dxt.cpp are routed through ArmPL when available, with scaling applied only when needed.
- Test error thresholds in test_dxt.cpp are relaxed (from 1e-5 to 2e-4 for float ) to account for numerical differences between ArmPL and OpenCV's reference DFT results.
**Performance Benchmarks :**
<img width="993" height="835" alt="image" src="https://github.com/user-attachments/assets/76def647-6d20-4bce-8bc9-7363e723669f" />
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- [x] The PR is proposed to the proper branch
core : add NEON intrinsics support for norm_mask function #28610
- This PR adds NEON intrinsics-based implementations for masked norm operations in norm.simd.hpp for ARM64 architecture.
- The optimized implementation uses ARM NEON intrinsics to accelerate masked norm computations (Infinity norm, L1 norm, and L2 norm) used by the norm function when a mask is provided.
- In the x64 architecture, masked norm operations benefit from IPP-based optimized implementations. However, on ARM64, the execution falls back to scalar implementations, which results in lower performance.
- To achieve performance parity with x64, NEON-based SIMD implementations have been added for ARM64.
- Additionally, scalar loop unrolling optimizations have been added for non-masked norm operations.
- After introducing these changes, masked norm operations showed significant performance improvements on ARM64 platforms, particularly for single-channel (cn=1) operations where NEON intrinsics provide the greatest benefit.
<img width="952" height="822" alt="image" src="https://github.com/user-attachments/assets/12d35f93-a316-4520-9d9c-12ce6b371ddb" />
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The previous OpenCL implementation of UMat::diag() relied on a sequence of
operations involving buffer initialization followed by copy/transpose on
an aliased diag() view. Although these operations were enqueued on an
in-order command queue, this implicitly assumed memory visibility between
kernels operating on aliased regions of the same buffer.
According to the OpenCL specification, in-order command queues only guarantee
command scheduling order, while memory visibility between commands is only
established through explicit command-level synchronization points (e.g.
events, barriers, or clFinish).Under OpenCL’s relaxed memory model, such
assumptions are not guaranteed without an explicit command-level synchronization
point, and can lead to data races and incorrect results, especially for very
small matrices (e.g. 1x1). The issue is more likely to be exposed on Mesa-based drivers
when the GPU is running at lower frequencies (e.g. 500 MHz).
This change introduces a dedicated OpenCL kernel to construct the diagonal
matrix in a single kernel invocation, avoiding intermediate aliasing and
eliminating the need for implicit ordering assumptions. If the OpenCL path
is unavailable or unsupported, the implementation transparently falls back
to the CPU path.
Signed-off-by: jiajia Qian <jiajia.qian@nxp.com>
The minMaxIdx dispatch table in modules/core/src/minmax.cpp stored
seven differently typed functions through C-style casts to a single
MinMaxIdxFunc pointer type, which is undefined behaviour and trips
UBSan's -fsanitize=function for any CV_32F or CV_64F input. This
change switches the typedef and every depth-specific helper to take
void pointers for src, minval and maxval, with the original typed
pointer recovered at function entry. The dispatch table no longer
needs C-style casts and the int pointer punning at the call site
goes away. Fixes#28928.
Better AutoBuffer API #28909
Mimic std::vector<> to help replacing std::vector<T> by cv::AutoBuffer<T> when possible
### Pull Request Readiness Checklist
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- Replace unsafe pointer arithmetic and direct buffer modification with std::string methods.
- Update documentation to clarify that the last digit is used as compression level and truncated from the actual filename.
- Add test cases for .gz and .gz0-9
doc: modernize Doxygen comments to support for v1.15.0 #28903
This PR addresses several documentation build failures encountered with modern Doxygen versions, particularly v1.15.0 (shipped with Ubuntu 26.04).
- flann module: Updated license headers from /**** to /*M****. This prevents Doxygen from misinterpreting the license text (specifically the unclosed backticks in ``AS IS'') as documentation blocks, which previously caused "Reached end of file" errors.
- core module: Fixed a typo in operations.hpp where a doubled backtick (``) caused parsing to fail.
- tutorials: Fixed a missing backtick in real_time_pose.markdown (around line 108) and corrected typos in the RobustMatcher class name.
- Links: Resolved explicit link request failures in calib3d.hpp by ensuring proper namespace resolution.
These fixes ensure that the documentation can be generated without errors on the latest toolchains.
### Pull Request Readiness Checklist
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- Emscripten 5.0.1+ changed version macros to uppercase and deprecated lowercase ones.
- Updated CMake to detect the version from both cases.
- Added macro aliases in intrin_wasm.hpp to avoid deprecated warnings and ensure compatibility.
Previously, OpenCL in-place flip kernels (rows/cols/both) could produce
incorrect results compared to the CPU implementation on strict OpenCL
drivers such as Mesa. The kernels relied on implicit load–load–store–store
(LLSS) ordering when src and dst alias, which is not guaranteed by the
OpenCL memory model and may be reordered.
Some vendor drivers happened to preserve the expected ordering, masking
the issue, but Mesa correctly exposes the undefined behavior.
This change introduces dedicated in-place flip kernels that:
- Explicitly detect in-place execution (src == dst)
- Stage data through local memory tiles
- Enforce correct ordering with work-group barriers
- Avoid global memory read/write aliasing hazards
The non in-place path is unchanged.
With this fix, OpenCL in-place flip produces correct and consistent results
across drivers, matches CPU behavior, and complies with the OpenCL memory
model.
Signed-off-by: jiajia Qian <jiajia.qian@nxp.com>
core(opencl): fix inplace transpose race by enforcing LLSS ordering via local barrier #28686
The former inplace transpose implementation allowed a reordering of global-memory operations across work-items. Specifically, the intended LLSS (Load–Load–Store–Store) access pattern could be reordered by the GPU into LSLS (Load–Store–Load–Store), causing partially written tiles to be observed by other work-items and producing incorrect output.
This patch introduces a tiled LDS-based algorithm and adds an explicit:
barrier(CLK_LOCAL_MEM_FENCE);
between the load and store phases.
### Pull Request Readiness Checklist
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core: add NEON implementation for rotate function #28609
- This PR adds a NEON intrinsics-based implementation for the rotate function in matrix_transform.cpp for Windows-ARM64.
- The optimized implementation uses ARM NEON intrinsics to accelerate the internal transpose step used by the rotate function.
- In the x64 architecture, the rotate operation benefits from IPP-based optimized implementations. However, on ARM64, the execution falls back to the scalar implementation, which results in lower performance.
- To achieve performance parity with x64, a NEON-based SIMD implementation has been added for ARM64.
- After introducing these changes, the rotate function showed noticeable performance improvements on ARM64 platforms.
<img width="1009" height="817" alt="image" src="https://github.com/user-attachments/assets/8bec0041-b19c-4fc8-9103-532746224515" />
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Fixes#28396 : out-of-bounds read in SIMD type conversion #28397Fixes#28396Fixes#27080
The vx_load_expand function in WASM intrinsics was using
wasm_v128_load which always loads a full 128-bit register
(16 bytes), even when the function only needed 8 elements.
For example, when converting uint8 to float32:
- vx_load_expand needs 8 uint8 elements
- But wasm_v128_load reads 16 bytes from memory
- This causes an 8-byte out-of-bounds read
### Pull Request Readiness Checklist
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Pratham Kumar
Pierre Chatelier
Alexander Smorkalov
Alexander Smorkalov
uwezkhan
Kumataro
Srujan rai
胡晨宇
Vincent Rabaud
Tiansuanyu
Adrian Kretz
kevinylin88
Teddy-Yangjiale
Maksim Shabunin
jiajia Qian
Samaresh Kumar Singh
kjg0724
Lurie97
Anshu
Abhishek Gola
usernotfound-101