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nishith-fujitsu 8efc0fd47b Merge pull request #28055 from nishith-fujitsu:sve_fastGEMM1t 
dnn: add SVE optimized fastGEMM1T function and SVE dispatch #28055

### Pull Request Readiness Checklist

See details at https://github.com/opencv/opencv/wiki/How_to_contribute#making-a-good-pull-request

- [x] I agree to contribute to the project under Apache 2 License.
- [x] To the best of my knowledge, the proposed patch is not based on a code under GPL or another license that is incompatible with OpenCV
- [x] The PR is proposed to the proper branch

**Description**
This PR enables fastGemm1t vectorized with SVE for AARCH64 architecture that called by recurrent layers and fully connected layers with SVE dispatching mechanism.

**ARM Compatibility:**
Modified the build scripts, and configuration files to ensure compatibility with ARM processors.

**Checklist**

Code changes have been tested on ARM devices (Graviton3).

**Modifications**

- Implemented FastGemm1T kernel in SVE with Vector length agnostic approach.

- Added Flags and checks to call our ported Kernel in Recurrent Layer and FullyConnected layer.

- Changes made to cmakelist.txt to dispatch our ported kernel for SVE.

- Flag OpenCV Dispatch with SVE optimization is added to support SVE implemented kernel for OpenCV. According to OpenCV build optimization https://github.com/opencv/opencv/wiki/CPU-optimizations-build-options 
cmake \
    -DCPU_BASELINE=NEON\
    -D CPU_DISPATCH=SVE\

**Performance Improvement**
- The suggested optimizations Improves the performance of LSTM layer and fully connected layer.
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Name of Test | dnn_neon | dnn_sve | dnn_sve   vs dnn_neon(x-factor)
-- | -- | -- | --
lstm::Layer_LSTM::BATCH=1,   IN=64, HIDDEN=192, TS=100 | 2.878 | 2.326 | 1.24
lstm::Layer_LSTM::BATCH=1,   IN=192, HIDDEN=192, TS=100 | 4.162 | 3.08 | 1.35
lstm::Layer_LSTM::BATCH=1,   IN=192, HIDDEN=512, TS=100 | 18.627 | 16.152 | 1.15
lstm::Layer_LSTM::BATCH=1,   IN=1024, HIDDEN=192, TS=100 | 10.98 | 7.976 | 1.38
lstm::Layer_LSTM::BATCH=64,   IN=64, HIDDEN=192, TS=2 | 4.41 | 3.459 | 1.27
lstm::Layer_LSTM::BATCH=64,   IN=192, HIDDEN=192, TS=2 | 6.567 | 4.807 | 1.37
lstm::Layer_LSTM::BATCH=64,   IN=192, HIDDEN=512, TS=2 | 28.471 | 22.909 | 1.24
lstm::Layer_LSTM::BATCH=64,   IN=1024, HIDDEN=192, TS=2 | 15.491 | 12.537 | 1.24
lstm::Layer_LSTM::BATCH=128,   IN=64, HIDDEN=192, TS=2 | 8.848 | 6.821 | 1.3
lstm::Layer_LSTM::BATCH=128,   IN=192, HIDDEN=192, TS=2 | 12.969 | 9.522 | 1.36
lstm::Layer_LSTM::BATCH=128,   IN=192, HIDDEN=512, TS=2 | 55.52 | 45.746 | 1.21
lstm::Layer_LSTM::BATCH=128,   IN=1024, HIDDEN=192, TS=2 | 31.226 | 26.132 | 1.19

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Name of Test | dnn_neon | dnn_sve | dnn_sve   vs dnn_neon(x-factor)
-- | -- | -- | --
fc::Layer_FullyConnected::([5,   16, 512, 128], 256, false, OCV/CPU) | 5.086 | 4.483 | 1.13
fc::Layer_FullyConnected::([5,   16, 512, 128], 256, true, OCV/CPU) | 8.512 | 8.347 | 1.02
fc::Layer_FullyConnected::([5,   16, 512, 128], 512, false, OCV/CPU) | 9.467 | 8.965 | 1.06
fc::Layer_FullyConnected::([5,   16, 512, 128], 512, true, OCV/CPU) | 14.855 | 13.527 | 1.1
fc::Layer_FullyConnected::([5,   16, 512, 128], 1024, false, OCV/CPU) | 18.821 | 18.023 | 1.04
fc::Layer_FullyConnected::([5,   16, 512, 128], 1024, true, OCV/CPU) | 27.558 | 24.966 | 1.1
fc::Layer_FullyConnected::([5,   512, 384, 0], 256, false, OCV/CPU) | 0.924 | 0.804 | 1.15
fc::Layer_FullyConnected::([5,   512, 384, 0], 256, true, OCV/CPU) | 1.259 | 1.126 | 1.12
fc::Layer_FullyConnected::([5,   512, 384, 0], 512, false, OCV/CPU) | 1.957 | 1.655 | 1.18
fc::Layer_FullyConnected::([5,   512, 384, 0], 512, true, OCV/CPU) | 2.831 | 2.775 | 1.02
fc::Layer_FullyConnected::([5,   512, 384, 0], 1024, false, OCV/CPU) | 5.92 | 6.379 | 0.93
fc::Layer_FullyConnected::([5,   512, 384, 0], 1024, true, OCV/CPU) | 8.924 | 8.993 | 0.99

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 2025-12-03 10:42:28 +03:00
Maksim Shabunin 4c81e174bf Merge pull request #25901 from mshabunin:fix-riscv-aarch-baseline 
RISC-V/AArch64: disable CPU features detection #25901

This PR is the first step in fixing current issues with NEON/RVV, FP16, BF16 and other CPU features on AArch64 and RISC-V platforms.

On AArch64 and RISC-V platforms we usually have the platform set by default in the toolchain when we compile it or in the cmake toolchain file or in CMAKE_CXX_FLAGS by user. Then, there are two ways to set platform options: a) "-mcpu=<some_cpu>" ; b) "-march=<arch description>" (e.g. "rv64gcv"). Furthermore, there are no similar "levels" of optimizations as for x86_64, instead we have features (RVV, FP16,...) which can be enabled or disabled. So, for example, if a user has "rv64gc" set by the toolchain and we want to enable RVV. Then we need to somehow parse their current feature set and append "v" (vector optimizations) to this string. This task is quite hard and the whole procedure is prone to errors.

I propose to use "CPU_BASELINE=DETECT" by default on AArch64 and RISC-V platforms. And somehow remove other features or make them read-only/detect-only, so that OpenCV wouldn't add any extra "-march" flags to the default configuration. We would rely only on the flags provided by the compiler and cmake toolchain file. We can have some predefined configurations in our cmake toolchain files.

Changes made by this PR:
- `CMakeLists.txt`: 
  - use `CMAKE_CROSSCOMPILING` instead of `CMAKE_TOOLCHAIN_FILE` to detect cross-compilation. This might be useful in cases of native compilation with a toolchain file
  - removed obsolete variables `ENABLE_NEON` and `ENABLE_VFPV3`, the first one have been turned ON by default on AArch64 platform which caused setting `CPU_BASELINE=NEON`
  - raise minimum cmake version allowed to 3.7 to allow using `CMAKE_CXX_FLAGS_INIT` in toolchain files
- added separate files with arch flags for native compilation on AArch64 and RISC-V, these files will be used in our toolchain files and in regular cmake
- use `DETECT` as default value for `CPU_BASELINE` also allow `NATIVE`, warn user if other values were used (only for AArch64 and RISC-V)
- for each feature listed in `CPU_DISPATCH` check if corresponding `CPU_${opt}_FLAGS_ON` has been provided, warn user if it is empty (only for AArch64 and RISC-V)
- use `CPU_BASELINE_DISABLE` variable to actually turn off macros responsible for corresponding features even if they are enabled by compiler
- removed Aarch64 feature merge procedure (it didn't support `-mcpu` and built-in `-march`)
- reworked AArch64 and two RISC-V cmake toolchain files (does not affect Android/OSX/iOS/Win):
  - use `CMAKE_CXX_FLAGS_INIT` to set compiler flags
  - use variables `ENABLE_BF16`, `ENABLE_DOTPROD`, `ENABLE_RVV`, `ENABLE_FP16` to control `-march`
  - AArch64: removed other compiler and linker flags
    - `-fdata-sections`, `-fsigned-char`, `-Wl,--no-undefined`, `-Wl,--gc-sections`   - already set by OpenCV
    - `-Wa,--noexecstack`, `-Wl,-z,noexecstack`, `-Wl,-z,relro`, `-Wl,-z,now` - can be enabled by OpenCV via `ENABLE_HARDENING`
    - `-Wno-psabi` - this option used to disable some warnings on older ARM platforms, shouldn't harm
  - ARM: removed same common flags as for AArch64, but left `-mthumb` and `--fix-cortex-a8`, `-z nocopyreloc`
 2024-09-12 18:07:24 +03:00