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Merge pull request #16236 from alalek:fix_core_simd_emulator

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* core: fix intrin_cpp, allow to build modules with SIMD emulator

* core(arithm): fix v_zero initialization

* core(simd): 'strict' types for binary/bitwise operations

* features2d: avoid aligned load issue in GCC 5.4 with emulated SIMD

* core(simd): alignment checks in SIMD emulator
This commit is contained in:
Alexander Alekhin
2020-01-10 21:31:02 +03:00
committed by GitHub
parent c75d93337e
commit e180cc050b
10 changed files with 320 additions and 109 deletions
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modules/core/src/arithm.cpp
+2 -1
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@@ -1522,7 +1522,8 @@ struct InRange_SIMD<float>
v_float32 low2 = vx_load(src2 + x + v_float32::nlanes);
v_float32 high2 = vx_load(src3 + x + v_float32::nlanes);
v_pack_store(dst + x, v_pack(v_reinterpret_as_u32((values1 >= low1) & (high1 >= values1)), v_reinterpret_as_u32((values2 >= low2) & (high2 >= values2))));
v_pack_store(dst + x, v_pack(v_reinterpret_as_u32(values1 >= low1) & v_reinterpret_as_u32(high1 >= values1),
v_reinterpret_as_u32(values2 >= low2) & v_reinterpret_as_u32(high2 >= values2)));
}
vx_cleanup();
return x;
modules/core/src/arithm.simd.hpp
+3 -3
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@@ -1593,7 +1593,7 @@ struct op_div_f
{
static inline Tvec r(const Tvec& a, const Tvec& b)
{
const Tvec v_zero = Tvec();
const Tvec v_zero = vx_setall<typename Tvec::lane_type>(0);
return v_select(b == v_zero, v_zero, a / b);
}
static inline T1 r(T1 a, T1 b)
@@ -1620,7 +1620,7 @@ struct op_div_scale
}
static inline Tvec pre(const Tvec& denom, const Tvec& res)
{
const Tvec v_zero = Tvec();
const Tvec v_zero = vx_setall<typename Tvec::lane_type>(0);
return v_select(denom == v_zero, v_zero, res);
}
static inline T1 r(T1 a, T1 denom, const T2* scalar)
@@ -1860,7 +1860,7 @@ struct op_recip
}
static inline Tvec pre(const Tvec& denom, const Tvec& res)
{
const Tvec v_zero = Tvec();
const Tvec v_zero = vx_setall<typename Tvec::lane_type>(0);
return v_select(denom == v_zero, v_zero, res);
}
static inline T1 r(T1 denom, const T2* scalar)
modules/core/src/lapack.cpp
+4 -3
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@@ -916,8 +916,9 @@ double cv::invert( InputArray _src, OutputArray _dst, int method )
result = true;
d = 1./d;
#if CV_SIMD128
static const float CV_DECL_ALIGNED(16) inv[4] = { 0.f,-0.f,-0.f,0.f };
v_float32x4 s0 = (v_load_halves((const float*)srcdata, (const float*)(srcdata + srcstep)) * v_setall_f32((float)d)) ^ v_load((const float *)inv);//0123//3120
const float d_32f = (float)d;
const v_float32x4 d_vec(d_32f, -d_32f, -d_32f, d_32f);
v_float32x4 s0 = v_load_halves((const float*)srcdata, (const float*)(srcdata + srcstep)) * d_vec;//0123//3120
s0 = v_extract<3>(s0, v_combine_low(v_rotate_right<1>(s0), s0));
v_store_low((float*)dstdata, s0);
v_store_high((float*)(dstdata + dststep), s0);
@@ -946,7 +947,7 @@ double cv::invert( InputArray _src, OutputArray _dst, int method )
v_float64x2 s0 = v_load((const double*)srcdata) * det;
v_float64x2 s1 = v_load((const double*)(srcdata+srcstep)) * det;
v_float64x2 sm = v_extract<1>(s1, s0);//30
v_float64x2 ss = v_extract<1>(s0, s1) ^ v_setall_f64(-0.);//12
v_float64x2 ss = v_setall<double>(0) - v_extract<1>(s0, s1);//12
v_store((double*)dstdata, v_combine_low(sm, ss));//31
v_store((double*)(dstdata + dststep), v_combine_high(ss, sm));//20
#else
modules/core/src/mathfuncs_core.simd.hpp
+1 -1
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@@ -725,7 +725,7 @@ void log32f( const float *_x, float *y, int n )
yf0 = v_fma(v_cvt_f32(yi0), vln2, yf0);
v_float32 delta = v_reinterpret_as_f32(h0 == vx_setall_s32(510)) & vshift;
v_float32 delta = v_select(v_reinterpret_as_f32(h0 == vx_setall_s32(510)), vshift, vx_setall<float>(0));
xf0 = v_fma((v_reinterpret_as_f32(xi0) - v1), xf0, delta);
v_float32 zf0 = v_fma(xf0, vA0, vA1);