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https://github.com/opencv/opencv.git
synced 2026-07-31 00:03:03 +04:00
Fix spelling typos
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@@ -134,7 +134,7 @@ CV__DNN_INLINE_NS_BEGIN
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virtual void setOutShape(const MatShape &outTailShape = MatShape()) = 0;
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/** @deprecated Use flag `produce_cell_output` in LayerParams.
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* @brief Specifies either interpret first dimension of input blob as timestamp dimenion either as sample.
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* @brief Specifies either interpret first dimension of input blob as timestamp dimension either as sample.
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*
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* If flag is set to true then shape of input blob will be interpreted as [`T`, `N`, `[data dims]`] where `T` specifies number of timestamps, `N` is number of independent streams.
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* In this case each forward() call will iterate through `T` timestamps and update layer's state `T` times.
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@@ -84,7 +84,7 @@ namespace cv { namespace dnn { namespace cuda4dnn { namespace kernels {
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* Reasoning:
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* ----------
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* Suppose an item's indices in the output tensor is [o1, o2, ...]. The indices in the input
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* tensor will be [o1 + off1, o2 + off2, ...]. The rest of the elements in the input are igored.
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* tensor will be [o1 + off1, o2 + off2, ...]. The rest of the elements in the input are ignored.
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*
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* If the size of the first axis of the input and output tensor is unity, the input and output indices
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* for all the elements will be of the form be [0, o2 + off2, ...] and [0, o2, ...] respectively. Note that
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@@ -227,7 +227,7 @@ namespace cv { namespace dnn { namespace cuda4dnn { namespace csl { namespace cu
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if (std::is_same<T, half>::value)
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CUDA4DNN_CHECK_CUDNN(cudnnSetConvolutionMathType(descriptor, CUDNN_TENSOR_OP_MATH));
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} catch (...) {
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/* cudnnDestroyConvolutionDescriptor will not fail for a valid desriptor object */
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/* cudnnDestroyConvolutionDescriptor will not fail for a valid descriptor object */
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CUDA4DNN_CHECK_CUDNN(cudnnDestroyConvolutionDescriptor(descriptor));
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throw;
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}
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@@ -266,7 +266,7 @@ namespace cv { namespace dnn { namespace cuda4dnn { namespace csl {
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/** page-locks \p size_in_bytes bytes of memory starting from \p ptr_
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*
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* Pre-conditons:
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* Pre-conditions:
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* - host memory should be unregistered
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*/
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MemoryLockGuard(void* ptr_, std::size_t size_in_bytes) {
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@@ -33,7 +33,7 @@ namespace cv { namespace dnn { namespace cuda4dnn { namespace csl {
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*
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* A `DevicePtr<T>` can implicitly convert to `DevicePtr<const T>`.
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*
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* Specalizations:
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* Specializations:
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* - DevicePtr<void>/DevicePtr<const void> do not support pointer arithmetic (but relational operators are provided)
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* - any device pointer pointing to mutable memory is implicitly convertible to DevicePtr<void>
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* - any device pointer is implicitly convertible to DevicePtr<const void>
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@@ -67,7 +67,7 @@ namespace cv { namespace dnn { namespace cuda4dnn { namespace csl {
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*/
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template <class T>
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class Tensor {
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static_assert(std::is_standard_layout<T>::value, "T must staisfy StandardLayoutType");
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static_assert(std::is_standard_layout<T>::value, "T must satisfy StandardLayoutType");
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public:
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using value_type = typename ManagedPtr<T>::element_type;
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@@ -553,7 +553,7 @@ namespace cv { namespace dnn { namespace cuda4dnn { namespace csl {
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* - [start, end) represents a forward range containing the length of the axes in order
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* - the number of axis lengths must be less than or equal to the rank
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* - at most one axis length is allowed for length deduction
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* - the lengths provided must ensure that the total number of elements remains unchnged
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* - the lengths provided must ensure that the total number of elements remains unchanged
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*
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* Exception Guarantee: Strong
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*/
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@@ -898,7 +898,7 @@ namespace cv { namespace dnn { namespace cuda4dnn { namespace csl {
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* - [start, end) represents a forward range containing length of the axes in order starting from axis zero
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* - the number of axis lengths must be less than or equal to the tensor rank
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* - at most one axis length is allowed for length deduction
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* - the lengths provided must ensure that the total number of elements remains unchnged
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* - the lengths provided must ensure that the total number of elements remains unchanged
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*
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* Exception Guarantee: Strong
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*/
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@@ -35,7 +35,7 @@ namespace cv { namespace dnn { namespace cuda4dnn { namespace csl {
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* Pre-conditions:
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* - \p dest and \p src must have the same shape
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*
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* Exception Gaurantee: Basic
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* Exception Guarantee: Basic
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*/
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template <class T> inline
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void copy(const Stream& stream, TensorSpan<T> dest, TensorView<T> src) {
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@@ -50,7 +50,7 @@ namespace cv { namespace dnn { namespace cuda4dnn { namespace csl {
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* - \p A and \p B must meet the mathematical requirements for matrix multiplication
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* - \p result must be large enough to hold the result
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*
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* Exception Gaurantee: Basic
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* Exception Guarantee: Basic
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*/
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template <class T> inline
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void gemm(const cublas::Handle& handle, T beta, TensorSpan<T> result, T alpha, bool transa, TensorView<T> A, bool transb, TensorView<T> B) {
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@@ -108,7 +108,7 @@ namespace cv { namespace dnn { namespace cuda4dnn { namespace csl {
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* Pre-conditions:
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* - \p A and \p result must be compatible tensors
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*
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* Exception Gaurantee: Basic
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* Exception Guarantee: Basic
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*/
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template <class T> inline
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void softmax(const cudnn::Handle& handle, TensorSpan<T> output, TensorView<T> input, int channel_axis, bool log) {
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@@ -103,7 +103,7 @@ namespace cv { namespace dnn { namespace cuda4dnn {
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CV_Assert(pooling_order == pads_end.size());
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/* cuDNN rounds down by default; hence, if ceilMode is false, we do nothing
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* otherwise, we add extra padding towards the end so that the convolution arithmetic yeilds
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* otherwise, we add extra padding towards the end so that the convolution arithmetic yields
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* the correct output size without having to deal with fancy fractional sizes
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*/
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auto pads_end_modified = pads_end;
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@@ -622,7 +622,7 @@ void InfEngineNgraphNet::forward(const std::vector<Ptr<BackendWrapper> >& outBlo
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try {
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wrapper->outProms[processedOutputs].setException(std::current_exception());
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} catch(...) {
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CV_LOG_ERROR(NULL, "DNN: Exception occured during async inference exception propagation");
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CV_LOG_ERROR(NULL, "DNN: Exception occurred during async inference exception propagation");
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}
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}
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}
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@@ -635,7 +635,7 @@ void InfEngineNgraphNet::forward(const std::vector<Ptr<BackendWrapper> >& outBlo
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try {
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wrapper->outProms[processedOutputs].setException(e);
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} catch(...) {
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CV_LOG_ERROR(NULL, "DNN: Exception occured during async inference exception propagation");
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CV_LOG_ERROR(NULL, "DNN: Exception occurred during async inference exception propagation");
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}
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}
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}
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@@ -116,7 +116,7 @@ message AttributeProto {
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// The type field MUST be present for this version of the IR.
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// For 0.0.1 versions of the IR, this field was not defined, and
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// implementations needed to use has_field hueristics to determine
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// implementations needed to use has_field heuristics to determine
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// which value field was in use. For IR_VERSION 0.0.2 or later, this
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// field MUST be set and match the f|i|s|t|... field in use. This
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// change was made to accommodate proto3 implementations.
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@@ -323,7 +323,7 @@ message TensorProto {
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// For float and complex64 values
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// Complex64 tensors are encoded as a single array of floats,
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// with the real components appearing in odd numbered positions,
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// and the corresponding imaginary component apparing in the
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// and the corresponding imaginary component appearing in the
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// subsequent even numbered position. (e.g., [1.0 + 2.0i, 3.0 + 4.0i]
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// is encoded as [1.0, 2.0 ,3.0 ,4.0]
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// When this field is present, the data_type field MUST be FLOAT or COMPLEX64.
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@@ -373,7 +373,7 @@ message TensorProto {
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// For double
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// Complex64 tensors are encoded as a single array of doubles,
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// with the real components appearing in odd numbered positions,
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// and the corresponding imaginary component apparing in the
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// and the corresponding imaginary component appearing in the
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// subsequent even numbered position. (e.g., [1.0 + 2.0i, 3.0 + 4.0i]
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// is encoded as [1.0, 2.0 ,3.0 ,4.0]
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// When this field is present, the data_type field MUST be DOUBLE or COMPLEX128
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@@ -350,7 +350,7 @@ namespace cv { namespace dnn {
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private:
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/* The same tensor memory can be reused by different layers whenever possible.
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* Hence, it is possible for different backend warppers to point to the same memory.
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* Hence, it is possible for different backend wrappers to point to the same memory.
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* However, it may use only a part of that memory and have a different shape.
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*
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* We store the common information such as device tensor and its corresponding host memory in
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@@ -243,7 +243,7 @@ Context::Context()
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queueCreateInfo.sType = VK_STRUCTURE_TYPE_DEVICE_QUEUE_CREATE_INFO;
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queueCreateInfo.queueFamilyIndex = kQueueFamilyIndex;
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queueCreateInfo.queueCount = 1; // create one queue in this family. We don't need more.
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float queuePriorities = 1.0; // we only have one queue, so this is not that imporant.
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float queuePriorities = 1.0; // we only have one queue, so this is not that important.
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queueCreateInfo.pQueuePriorities = &queuePriorities;
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VkDeviceCreateInfo deviceCreateInfo = {};
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