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mirror of https://github.com/opencv/opencv.git synced 2026-07-31 00:03:03 +04:00

Fix spelling typos

This commit is contained in:
Brian Wignall
2019-12-26 06:45:03 -05:00
parent 89d3f95a8e
commit 659ffaddb4
110 changed files with 142 additions and 142 deletions
@@ -134,7 +134,7 @@ CV__DNN_INLINE_NS_BEGIN
virtual void setOutShape(const MatShape &outTailShape = MatShape()) = 0;
/** @deprecated Use flag `produce_cell_output` in LayerParams.
* @brief Specifies either interpret first dimension of input blob as timestamp dimenion either as sample.
* @brief Specifies either interpret first dimension of input blob as timestamp dimension either as sample.
*
* If flag is set to true then shape of input blob will be interpreted as [`T`, `N`, `[data dims]`] where `T` specifies number of timestamps, `N` is number of independent streams.
* In this case each forward() call will iterate through `T` timestamps and update layer's state `T` times.
+1 -1
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@@ -84,7 +84,7 @@ namespace cv { namespace dnn { namespace cuda4dnn { namespace kernels {
* Reasoning:
* ----------
* Suppose an item's indices in the output tensor is [o1, o2, ...]. The indices in the input
* tensor will be [o1 + off1, o2 + off2, ...]. The rest of the elements in the input are igored.
* tensor will be [o1 + off1, o2 + off2, ...]. The rest of the elements in the input are ignored.
*
* If the size of the first axis of the input and output tensor is unity, the input and output indices
* for all the elements will be of the form be [0, o2 + off2, ...] and [0, o2, ...] respectively. Note that
@@ -227,7 +227,7 @@ namespace cv { namespace dnn { namespace cuda4dnn { namespace csl { namespace cu
if (std::is_same<T, half>::value)
CUDA4DNN_CHECK_CUDNN(cudnnSetConvolutionMathType(descriptor, CUDNN_TENSOR_OP_MATH));
} catch (...) {
/* cudnnDestroyConvolutionDescriptor will not fail for a valid desriptor object */
/* cudnnDestroyConvolutionDescriptor will not fail for a valid descriptor object */
CUDA4DNN_CHECK_CUDNN(cudnnDestroyConvolutionDescriptor(descriptor));
throw;
}
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@@ -266,7 +266,7 @@ namespace cv { namespace dnn { namespace cuda4dnn { namespace csl {
/** page-locks \p size_in_bytes bytes of memory starting from \p ptr_
*
* Pre-conditons:
* Pre-conditions:
* - host memory should be unregistered
*/
MemoryLockGuard(void* ptr_, std::size_t size_in_bytes) {
+1 -1
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@@ -33,7 +33,7 @@ namespace cv { namespace dnn { namespace cuda4dnn { namespace csl {
*
* A `DevicePtr<T>` can implicitly convert to `DevicePtr<const T>`.
*
* Specalizations:
* Specializations:
* - DevicePtr<void>/DevicePtr<const void> do not support pointer arithmetic (but relational operators are provided)
* - any device pointer pointing to mutable memory is implicitly convertible to DevicePtr<void>
* - any device pointer is implicitly convertible to DevicePtr<const void>
+3 -3
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@@ -67,7 +67,7 @@ namespace cv { namespace dnn { namespace cuda4dnn { namespace csl {
*/
template <class T>
class Tensor {
static_assert(std::is_standard_layout<T>::value, "T must staisfy StandardLayoutType");
static_assert(std::is_standard_layout<T>::value, "T must satisfy StandardLayoutType");
public:
using value_type = typename ManagedPtr<T>::element_type;
@@ -553,7 +553,7 @@ namespace cv { namespace dnn { namespace cuda4dnn { namespace csl {
* - [start, end) represents a forward range containing the length of the axes in order
* - the number of axis lengths must be less than or equal to the rank
* - at most one axis length is allowed for length deduction
* - the lengths provided must ensure that the total number of elements remains unchnged
* - the lengths provided must ensure that the total number of elements remains unchanged
*
* Exception Guarantee: Strong
*/
@@ -898,7 +898,7 @@ namespace cv { namespace dnn { namespace cuda4dnn { namespace csl {
* - [start, end) represents a forward range containing length of the axes in order starting from axis zero
* - the number of axis lengths must be less than or equal to the tensor rank
* - at most one axis length is allowed for length deduction
* - the lengths provided must ensure that the total number of elements remains unchnged
* - the lengths provided must ensure that the total number of elements remains unchanged
*
* Exception Guarantee: Strong
*/
+3 -3
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@@ -35,7 +35,7 @@ namespace cv { namespace dnn { namespace cuda4dnn { namespace csl {
* Pre-conditions:
* - \p dest and \p src must have the same shape
*
* Exception Gaurantee: Basic
* Exception Guarantee: Basic
*/
template <class T> inline
void copy(const Stream& stream, TensorSpan<T> dest, TensorView<T> src) {
@@ -50,7 +50,7 @@ namespace cv { namespace dnn { namespace cuda4dnn { namespace csl {
* - \p A and \p B must meet the mathematical requirements for matrix multiplication
* - \p result must be large enough to hold the result
*
* Exception Gaurantee: Basic
* Exception Guarantee: Basic
*/
template <class T> inline
void gemm(const cublas::Handle& handle, T beta, TensorSpan<T> result, T alpha, bool transa, TensorView<T> A, bool transb, TensorView<T> B) {
@@ -108,7 +108,7 @@ namespace cv { namespace dnn { namespace cuda4dnn { namespace csl {
* Pre-conditions:
* - \p A and \p result must be compatible tensors
*
* Exception Gaurantee: Basic
* Exception Guarantee: Basic
*/
template <class T> inline
void softmax(const cudnn::Handle& handle, TensorSpan<T> output, TensorView<T> input, int channel_axis, bool log) {
@@ -103,7 +103,7 @@ namespace cv { namespace dnn { namespace cuda4dnn {
CV_Assert(pooling_order == pads_end.size());
/* cuDNN rounds down by default; hence, if ceilMode is false, we do nothing
* otherwise, we add extra padding towards the end so that the convolution arithmetic yeilds
* otherwise, we add extra padding towards the end so that the convolution arithmetic yields
* the correct output size without having to deal with fancy fractional sizes
*/
auto pads_end_modified = pads_end;
+2 -2
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@@ -622,7 +622,7 @@ void InfEngineNgraphNet::forward(const std::vector<Ptr<BackendWrapper> >& outBlo
try {
wrapper->outProms[processedOutputs].setException(std::current_exception());
} catch(...) {
CV_LOG_ERROR(NULL, "DNN: Exception occured during async inference exception propagation");
CV_LOG_ERROR(NULL, "DNN: Exception occurred during async inference exception propagation");
}
}
}
@@ -635,7 +635,7 @@ void InfEngineNgraphNet::forward(const std::vector<Ptr<BackendWrapper> >& outBlo
try {
wrapper->outProms[processedOutputs].setException(e);
} catch(...) {
CV_LOG_ERROR(NULL, "DNN: Exception occured during async inference exception propagation");
CV_LOG_ERROR(NULL, "DNN: Exception occurred during async inference exception propagation");
}
}
}
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@@ -116,7 +116,7 @@ message AttributeProto {
// The type field MUST be present for this version of the IR.
// For 0.0.1 versions of the IR, this field was not defined, and
// implementations needed to use has_field hueristics to determine
// implementations needed to use has_field heuristics to determine
// which value field was in use. For IR_VERSION 0.0.2 or later, this
// field MUST be set and match the f|i|s|t|... field in use. This
// change was made to accommodate proto3 implementations.
@@ -323,7 +323,7 @@ message TensorProto {
// For float and complex64 values
// Complex64 tensors are encoded as a single array of floats,
// with the real components appearing in odd numbered positions,
// and the corresponding imaginary component apparing in the
// and the corresponding imaginary component appearing in the
// subsequent even numbered position. (e.g., [1.0 + 2.0i, 3.0 + 4.0i]
// is encoded as [1.0, 2.0 ,3.0 ,4.0]
// When this field is present, the data_type field MUST be FLOAT or COMPLEX64.
@@ -373,7 +373,7 @@ message TensorProto {
// For double
// Complex64 tensors are encoded as a single array of doubles,
// with the real components appearing in odd numbered positions,
// and the corresponding imaginary component apparing in the
// and the corresponding imaginary component appearing in the
// subsequent even numbered position. (e.g., [1.0 + 2.0i, 3.0 + 4.0i]
// is encoded as [1.0, 2.0 ,3.0 ,4.0]
// When this field is present, the data_type field MUST be DOUBLE or COMPLEX128
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@@ -350,7 +350,7 @@ namespace cv { namespace dnn {
private:
/* The same tensor memory can be reused by different layers whenever possible.
* Hence, it is possible for different backend warppers to point to the same memory.
* Hence, it is possible for different backend wrappers to point to the same memory.
* However, it may use only a part of that memory and have a different shape.
*
* We store the common information such as device tensor and its corresponding host memory in
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@@ -243,7 +243,7 @@ Context::Context()
queueCreateInfo.sType = VK_STRUCTURE_TYPE_DEVICE_QUEUE_CREATE_INFO;
queueCreateInfo.queueFamilyIndex = kQueueFamilyIndex;
queueCreateInfo.queueCount = 1; // create one queue in this family. We don't need more.
float queuePriorities = 1.0; // we only have one queue, so this is not that imporant.
float queuePriorities = 1.0; // we only have one queue, so this is not that important.
queueCreateInfo.pQueuePriorities = &queuePriorities;
VkDeviceCreateInfo deviceCreateInfo = {};