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fix exp, log | enable ui for log | strengthen test

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Co-authored-by: Liutong HAN <liutong2020@iscas.ac.cn>
This commit is contained in:
GenshinImpactStarts
2025-03-06 10:00:35 +00:00
parent 524d8ae01c
commit 0fed1fa184
6 changed files with 39 additions and 15 deletions
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modules/core/include/opencv2/core/hal/intrin_rvv_scalable.hpp
+22
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@@ -509,6 +509,28 @@ inline v_float64 v_lut(const double* tab, const v_int32& vidx) \
#endif
// Strangely, __riscv_vluxseg2ei32 is slower (tested on Muse-Pi and CanMV K230)
#define OPENCV_HAL_IMPL_RVV_LUT_DEINTERLEAVE(_Tpvec, _Tp, suffix) \
inline void v_lut_deinterleave(const _Tp* tab, const v_int32& vidx, _Tpvec& vx, _Tpvec& vy) \
{ \
v_uint32 vidx_ = __riscv_vmul(__riscv_vreinterpret_u32m2(vidx), sizeof(_Tp), VTraits<v_int32>::vlanes()); \
vx = __riscv_vluxei32(tab, vidx_, VTraits<_Tpvec>::vlanes()); \
vy = __riscv_vluxei32(tab, __riscv_vadd(vidx_, sizeof(_Tp), VTraits<v_int32>::vlanes()), VTraits<_Tpvec>::vlanes()); \
}
OPENCV_HAL_IMPL_RVV_LUT_DEINTERLEAVE(v_float32, float, f32)
OPENCV_HAL_IMPL_RVV_LUT_DEINTERLEAVE(v_int32, int, i32)
OPENCV_HAL_IMPL_RVV_LUT_DEINTERLEAVE(v_uint32, unsigned, u32)
#if CV_SIMD_SCALABLE_64F
inline void v_lut_deinterleave(const double* tab, const v_int32& vidx, v_float64& vx, v_float64& vy) \
{ \
vuint32m1_t vidx_ = __riscv_vmul(__riscv_vlmul_trunc_u32m1(__riscv_vreinterpret_u32m2(vidx)), sizeof(double), VTraits<v_float64>::vlanes()); \
vx = __riscv_vluxei32(tab, vidx_, VTraits<v_float64>::vlanes()); \
vy = __riscv_vluxei32(tab, __riscv_vadd(vidx_, sizeof(double), VTraits<v_int32>::vlanes()), VTraits<v_float64>::vlanes()); \
}
#endif
inline v_uint8 v_lut(const uchar* tab, const int* idx) { return v_reinterpret_as_u8(v_lut((schar*)tab, idx)); }
inline v_uint8 v_lut_pairs(const uchar* tab, const int* idx) { return v_reinterpret_as_u8(v_lut_pairs((schar*)tab, idx)); }
inline v_uint8 v_lut_quads(const uchar* tab, const int* idx) { return v_reinterpret_as_u8(v_lut_quads((schar*)tab, idx)); }
modules/core/src/mathfuncs_core.simd.hpp
+2 -2
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@@ -771,7 +771,7 @@ void log32f( const float *_x, float *y, int n )
int i = 0;
const int* x = (const int*)_x;
#if CV_SIMD
#if (CV_SIMD || CV_SIMD_SCALABLE)
const int VECSZ = VTraits<v_float32>::vlanes();
const v_float32 vln2 = vx_setall_f32((float)ln_2);
const v_float32 v1 = vx_setall_f32(1.f);
@@ -846,7 +846,7 @@ void log64f( const double *x, double *y, int n )
int i = 0;
#if CV_SIMD_64F
#if (CV_SIMD_64F || CV_SIMD_SCALABLE_64F)
const int VECSZ = VTraits<v_float64>::vlanes();
const v_float64 vln2 = vx_setall_f64(ln_2);
modules/core/test/test_arithm.cpp
+1 -1
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@@ -1099,7 +1099,7 @@ struct ExpOp : public BaseElemWiseOp
}
void getValueRange(int depth, double& minval, double& maxval)
{
maxval = depth == CV_32F ? 50 : 100;
maxval = depth == CV_32F ? 80 : 700;
minval = -maxval;
}
void op(const vector<Mat>& src, Mat& dst, const Mat&)
modules/core/test/test_hal_core.cpp
+2 -1
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@@ -74,7 +74,8 @@ TEST_P(mathfuncs, accuracy)
int n = 100;
Mat src(1, n, depth), dst(1, n, depth), dst0(1, n, depth);
randu(src, 1, 10);
double maxval = depth == CV_32F ? 80 : 700;
randu(src, -maxval, maxval);
switch (nfunc)
{