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Merge pull request #23980 from hanliutong:rewrite-core

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Rewrite Universal Intrinsic code by using new API: Core module. #23980

The goal of this PR is to match and modify all SIMD code blocks guarded by `CV_SIMD` macro in the `opencv/modules/core` folder and rewrite them by using the new Universal Intrinsic API.

The patch is almost auto-generated by using the [rewriter](https://github.com/hanliutong/rewriter), related PR #23885.

Most of the files have been rewritten, but I marked this PR as draft because, the `CV_SIMD` macro also exists in the following files, and the reasons why they are not rewrited are:

1. ~~code design for fixed-size SIMD (v_int16x8, v_float32x4, etc.), need to manually rewrite.~~ Rewrited
- ./modules/core/src/stat.simd.hpp
- ./modules/core/src/matrix_transform.cpp
- ./modules/core/src/matmul.simd.hpp

2. Vector types are wrapped in other class/struct, that are not supported by the compiler in variable-length backends. Can not be rewrited directly.
- ./modules/core/src/mathfuncs_core.simd.hpp 
```cpp
struct v_atan_f32
{
    explicit v_atan_f32(const float& scale)
    {
...
    }

    v_float32 compute(const v_float32& y, const v_float32& x)
    {
...
    }

...
    v_float32 val90; // sizeless type can not used in a class
    v_float32 val180;
    v_float32 val360;
    v_float32 s;
};
```

3. The API interface does not support/does not match

- ./modules/core/src/norm.cpp 
Use `v_popcount`, ~~waiting for #23966~~ Fixed
- ./modules/core/src/has_non_zero.simd.hpp
Use illegal Universal Intrinsic API: For float type, there is no logical operation `|`. Further discussion needed

```cpp
/** @brief Bitwise OR

Only for integer types. */
template<typename _Tp, int n> CV_INLINE v_reg<_Tp, n> operator|(const v_reg<_Tp, n>& a, const v_reg<_Tp, n>& b);
template<typename _Tp, int n> CV_INLINE v_reg<_Tp, n>& operator|=(v_reg<_Tp, n>& a, const v_reg<_Tp, n>& b);
```

```cpp
#if CV_SIMD
    typedef v_float32 v_type;
    const v_type v_zero = vx_setzero_f32();
    constexpr const int unrollCount = 8;
    int step = v_type::nlanes * unrollCount;
    int len0 = len & -step;
    const float* srcSimdEnd = src+len0;

    int countSIMD = static_cast<int>((srcSimdEnd-src)/step);
    while(!res && countSIMD--)
    {
        v_type v0 = vx_load(src);
        src += v_type::nlanes;
        v_type v1 = vx_load(src);
        src += v_type::nlanes;
....
        src += v_type::nlanes;
        v0 |= v1; //Illegal ?
....
        //res = v_check_any(((v0 | v4) != v_zero));//beware : (NaN != 0) returns "false" since != is mapped to _CMP_NEQ_OQ and not _CMP_NEQ_UQ
        res = !v_check_all(((v0 | v4) == v_zero));
    }

    v_cleanup();
#endif
```

### Pull Request Readiness Checklist

See details at https://github.com/opencv/opencv/wiki/How_to_contribute#making-a-good-pull-request

- [ ] I agree to contribute to the project under Apache 2 License.
- [ ] To the best of my knowledge, the proposed patch is not based on a code under GPL or another license that is incompatible with OpenCV
- [ ] The PR is proposed to the proper branch
- [ ] There is a reference to the original bug report and related work
- [ ] There is accuracy test, performance test and test data in opencv_extra repository, if applicable
      Patch to opencv_extra has the same branch name.
- [ ] The feature is well documented and sample code can be built with the project CMake
This commit is contained in:
HAN Liutong
2023-08-11 13:33:33 +08:00
committed by GitHub
parent 3421b950ce
commit 0dd7769bb1
17 changed files with 466 additions and 518 deletions
Download Patch File Download Diff File Expand all files Collapse all files
modules/core/src/arithm.cpp
+26 -26
View File
@@ -1332,7 +1332,7 @@ struct InRange_SIMD
}
};
#if CV_SIMD
#if (CV_SIMD || CV_SIMD_SCALABLE)
template <>
struct InRange_SIMD<uchar>
@@ -1341,7 +1341,7 @@ struct InRange_SIMD<uchar>
uchar * dst, int len) const
{
int x = 0;
const int width = v_uint8::nlanes;
const int width = VTraits<v_uint8>::vlanes();
for (; x <= len - width; x += width)
{
@@ -1349,7 +1349,7 @@ struct InRange_SIMD<uchar>
v_uint8 low = vx_load(src2 + x);
v_uint8 high = vx_load(src3 + x);
v_store(dst + x, (values >= low) & (high >= values));
v_store(dst + x, v_and(v_ge(values, low), v_ge(high, values)));
}
vx_cleanup();
return x;
@@ -1363,7 +1363,7 @@ struct InRange_SIMD<schar>
uchar * dst, int len) const
{
int x = 0;
const int width = v_int8::nlanes;
const int width = VTraits<v_int8>::vlanes();
for (; x <= len - width; x += width)
{
@@ -1371,7 +1371,7 @@ struct InRange_SIMD<schar>
v_int8 low = vx_load(src2 + x);
v_int8 high = vx_load(src3 + x);
v_store((schar*)(dst + x), (values >= low) & (high >= values));
v_store((schar*)(dst + x), v_and(v_ge(values, low), v_ge(high, values)));
}
vx_cleanup();
return x;
@@ -1385,7 +1385,7 @@ struct InRange_SIMD<ushort>
uchar * dst, int len) const
{
int x = 0;
const int width = v_uint16::nlanes * 2;
const int width = VTraits<v_uint16>::vlanes() * 2;
for (; x <= len - width; x += width)
{
@@ -1393,11 +1393,11 @@ struct InRange_SIMD<ushort>
v_uint16 low1 = vx_load(src2 + x);
v_uint16 high1 = vx_load(src3 + x);
v_uint16 values2 = vx_load(src1 + x + v_uint16::nlanes);
v_uint16 low2 = vx_load(src2 + x + v_uint16::nlanes);
v_uint16 high2 = vx_load(src3 + x + v_uint16::nlanes);
v_uint16 values2 = vx_load(src1 + x + VTraits<v_uint16>::vlanes());
v_uint16 low2 = vx_load(src2 + x + VTraits<v_uint16>::vlanes());
v_uint16 high2 = vx_load(src3 + x + VTraits<v_uint16>::vlanes());
v_store(dst + x, v_pack((values1 >= low1) & (high1 >= values1), (values2 >= low2) & (high2 >= values2)));
v_store(dst + x, v_pack(v_and(v_ge(values1, low1), v_ge(high1, values1)), v_and(v_ge(values2, low2), v_ge(high2, values2))));
}
vx_cleanup();
return x;
@@ -1411,7 +1411,7 @@ struct InRange_SIMD<short>
uchar * dst, int len) const
{
int x = 0;
const int width = (int)v_int16::nlanes * 2;
const int width = (int)VTraits<v_int16>::vlanes() * 2;
for (; x <= len - width; x += width)
{
@@ -1419,11 +1419,11 @@ struct InRange_SIMD<short>
v_int16 low1 = vx_load(src2 + x);
v_int16 high1 = vx_load(src3 + x);
v_int16 values2 = vx_load(src1 + x + v_int16::nlanes);
v_int16 low2 = vx_load(src2 + x + v_int16::nlanes);
v_int16 high2 = vx_load(src3 + x + v_int16::nlanes);
v_int16 values2 = vx_load(src1 + x + VTraits<v_int16>::vlanes());
v_int16 low2 = vx_load(src2 + x + VTraits<v_int16>::vlanes());
v_int16 high2 = vx_load(src3 + x + VTraits<v_int16>::vlanes());
v_store((schar*)(dst + x), v_pack((values1 >= low1) & (high1 >= values1), (values2 >= low2) & (high2 >= values2)));
v_store((schar*)(dst + x), v_pack(v_and(v_ge(values1, low1), v_ge(high1, values1)), v_and(v_ge(values2, low2), v_ge(high2, values2))));
}
vx_cleanup();
return x;
@@ -1437,7 +1437,7 @@ struct InRange_SIMD<int>
uchar * dst, int len) const
{
int x = 0;
const int width = (int)v_int32::nlanes * 2;
const int width = (int)VTraits<v_int32>::vlanes() * 2;
for (; x <= len - width; x += width)
{
@@ -1445,11 +1445,11 @@ struct InRange_SIMD<int>
v_int32 low1 = vx_load(src2 + x);
v_int32 high1 = vx_load(src3 + x);
v_int32 values2 = vx_load(src1 + x + v_int32::nlanes);
v_int32 low2 = vx_load(src2 + x + v_int32::nlanes);
v_int32 high2 = vx_load(src3 + x + v_int32::nlanes);
v_int32 values2 = vx_load(src1 + x + VTraits<v_int32>::vlanes());
v_int32 low2 = vx_load(src2 + x + VTraits<v_int32>::vlanes());
v_int32 high2 = vx_load(src3 + x + VTraits<v_int32>::vlanes());
v_pack_store(dst + x, v_reinterpret_as_u16(v_pack((values1 >= low1) & (high1 >= values1), (values2 >= low2) & (high2 >= values2))));
v_pack_store(dst + x, v_reinterpret_as_u16(v_pack(v_and(v_ge(values1, low1), v_ge(high1, values1)), v_and(v_ge(values2, low2), v_ge(high2, values2)))));
}
vx_cleanup();
return x;
@@ -1463,7 +1463,7 @@ struct InRange_SIMD<float>
uchar * dst, int len) const
{
int x = 0;
const int width = (int)v_float32::nlanes * 2;
const int width = (int)VTraits<v_float32>::vlanes() * 2;
for (; x <= len - width; x += width)
{
@@ -1471,12 +1471,12 @@ struct InRange_SIMD<float>
v_float32 low1 = vx_load(src2 + x);
v_float32 high1 = vx_load(src3 + x);
v_float32 values2 = vx_load(src1 + x + v_float32::nlanes);
v_float32 low2 = vx_load(src2 + x + v_float32::nlanes);
v_float32 high2 = vx_load(src3 + x + v_float32::nlanes);
v_float32 values2 = vx_load(src1 + x + VTraits<v_float32>::vlanes());
v_float32 low2 = vx_load(src2 + x + VTraits<v_float32>::vlanes());
v_float32 high2 = vx_load(src3 + x + VTraits<v_float32>::vlanes());
v_pack_store(dst + x, v_pack(v_reinterpret_as_u32(values1 >= low1) & v_reinterpret_as_u32(high1 >= values1),
v_reinterpret_as_u32(values2 >= low2) & v_reinterpret_as_u32(high2 >= values2)));
v_pack_store(dst + x, v_pack(v_and(v_reinterpret_as_u32(v_ge(values1, low1)), v_reinterpret_as_u32(v_ge(high1, values1))),
v_and(v_reinterpret_as_u32(v_ge(values2, low2)), v_reinterpret_as_u32(v_ge(high2, values2)))));
}
vx_cleanup();
return x;